Samsung Ramps up 64-Layer V-NAND Memory Production to Accommodate Expanding Line-up of High-Performance Flash Storage Solutions. Based on its success with 64-layer V-NAND, Samsung has secured the fundamental technology that it needs in the future to produce V-NAND chips with one terabit capacity and more, by stacking over 90 layers of cell.
At Flash Memory Summit this week, Samsung is sharing details of their storage technology roadmaps and showing off several prototypes. Last year, Samsung announced their fourth generation of 3D NAND, a 64-layer design. This fourth generation V-NAND is now in mass production and will be rolling out to many product segments over the coming months.
Most products will be using either 256Gb or 512Gb TLC dies. Compared to the 48-layer third generation V-NAND, the 64-layer V-NAND offers the same read performance but approximately 11% higher write performance. Power consumption has been improved more significantly, with the current required for a read operation dropping by 12% and for a program operation the current required has decreased by 25%. Samsung claims their 64-layer V-NAND in a TLC configuration can last for 7,000 to 20,000 program/erase cycles. Samsung has now also announced their fifth-generation V-NAND, which will increase the layer count further to 96 layers with relatively few other changes to the design.
The fifth generation will include Samsung's first QLC NAND flash (four bits per cell), with a capacity of 1Tb (128GB) per die. Beyond the fifth generation, Samsung says they may start using techniques like string stacking, putting the peripheral logic under the memory array, or shrinking the horizontal dimensions of their flash. String stacking is more or less inevitable if the layer count is to continue increasing, but it is not clear exactly when that transition will be worthwhile. At the moment, Samsung estimates string stacking would increase production costs by about 15% due to the extra process steps involved, and aligning a second stack of 3D NAND layers will present serious yield challenges. Putting the peripheral logic under the memory array has worked well for the 3D NAND from Intel and Micron, and Samsung estimates it could reduce their own die sizes by 20-30%. Shrinking the horizontal dimensions of their NAND flash memory cells also offers a way to increase density and improve price per GB, but that path leads to the same endurance and reliability problems that eventually made planar NAND a dead end technology. Samsung provided an update on Z-NAND memory, their near-term solution for offering lower latency than existing flash memory.
In the long run, non-flash persistent memory technologies will be required, but by modifying their existing 3D V-NAND architecture they have an SLC-based memory that offers 3µs read latencies, 15 times faster than their V-NAND flash memory (whether that's comparing against MLC or TLC V-NAND was not specified). Their first Z-NAND product, the Z-SSD SZ985, offers overall random read latencies of less than 15µs, which is 5.5 times faster than their TLC-based enterprise SSDs.
Samsung also announced a second generation Z-NAND, this time based on MLC NAND instead of SLC. This sacrifices a bit of performance (5µs read latency compared to 3µs) but offers much better storage density. Looking beyond Z-NAND for new memory technologies, Samsung is working on both phase-change memory and spin-torque magnetoresistive RAM (ST-MRAM). Samsung's SSD announcements based on the above V-NAND technologies include a 128TB 2.5' SAS SSD based on QLC V-NAND. For this drive, Samsung will be stacking 32 dies per package, for a total of 4TB in each BGA device. Samsung is also previewing a proposed new enterprise SSD form factor they are referring to as 'NGSFF' for now. Digital blue usb microscope drivers. This form factor uses a 30.5mm by 110mm PCB, substantially wider than the most commonly implemented M.2 form factors and wide enough to accommodate two rows of flash packages.
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Samsung Ramps up 64-Layer V-NAND Memory Production to Accommodate Expanding Line-up of High-Performance Flash Storage Solutions. Based on its success with 64-layer V-NAND, Samsung has secured the fundamental technology that it needs in the future to produce V-NAND chips with one terabit capacity and more, by stacking over 90 layers of cell.
At Flash Memory Summit this week, Samsung is sharing details of their storage technology roadmaps and showing off several prototypes. Last year, Samsung announced their fourth generation of 3D NAND, a 64-layer design. This fourth generation V-NAND is now in mass production and will be rolling out to many product segments over the coming months.
Most products will be using either 256Gb or 512Gb TLC dies. Compared to the 48-layer third generation V-NAND, the 64-layer V-NAND offers the same read performance but approximately 11% higher write performance. Power consumption has been improved more significantly, with the current required for a read operation dropping by 12% and for a program operation the current required has decreased by 25%. Samsung claims their 64-layer V-NAND in a TLC configuration can last for 7,000 to 20,000 program/erase cycles. Samsung has now also announced their fifth-generation V-NAND, which will increase the layer count further to 96 layers with relatively few other changes to the design.
The fifth generation will include Samsung's first QLC NAND flash (four bits per cell), with a capacity of 1Tb (128GB) per die. Beyond the fifth generation, Samsung says they may start using techniques like string stacking, putting the peripheral logic under the memory array, or shrinking the horizontal dimensions of their flash. String stacking is more or less inevitable if the layer count is to continue increasing, but it is not clear exactly when that transition will be worthwhile. At the moment, Samsung estimates string stacking would increase production costs by about 15% due to the extra process steps involved, and aligning a second stack of 3D NAND layers will present serious yield challenges. Putting the peripheral logic under the memory array has worked well for the 3D NAND from Intel and Micron, and Samsung estimates it could reduce their own die sizes by 20-30%. Shrinking the horizontal dimensions of their NAND flash memory cells also offers a way to increase density and improve price per GB, but that path leads to the same endurance and reliability problems that eventually made planar NAND a dead end technology. Samsung provided an update on Z-NAND memory, their near-term solution for offering lower latency than existing flash memory.
In the long run, non-flash persistent memory technologies will be required, but by modifying their existing 3D V-NAND architecture they have an SLC-based memory that offers 3µs read latencies, 15 times faster than their V-NAND flash memory (whether that's comparing against MLC or TLC V-NAND was not specified). Their first Z-NAND product, the Z-SSD SZ985, offers overall random read latencies of less than 15µs, which is 5.5 times faster than their TLC-based enterprise SSDs.
Samsung also announced a second generation Z-NAND, this time based on MLC NAND instead of SLC. This sacrifices a bit of performance (5µs read latency compared to 3µs) but offers much better storage density. Looking beyond Z-NAND for new memory technologies, Samsung is working on both phase-change memory and spin-torque magnetoresistive RAM (ST-MRAM). Samsung's SSD announcements based on the above V-NAND technologies include a 128TB 2.5' SAS SSD based on QLC V-NAND. For this drive, Samsung will be stacking 32 dies per package, for a total of 4TB in each BGA device. Samsung is also previewing a proposed new enterprise SSD form factor they are referring to as 'NGSFF' for now. Digital blue usb microscope drivers. This form factor uses a 30.5mm by 110mm PCB, substantially wider than the most commonly implemented M.2 form factors and wide enough to accommodate two rows of flash packages.